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f ed l620q130 - 0 2 issue date : may 12 , 201 6 ml620q1 3 1/2/3/4/5/6 16- bit micro controller 1 / 33 general description this lsi is a high performance cmos 16 - bit microcontroller equipped with an 16 - bit cpu nx - u16/100 and integrated with rich peripheral functions such as the timer, pwm, comparator, voltage level supervisor, uart, i2c, and successive appr oximation type a/d converter. the cpu nx - u16/100 is capable of efficient instruction execution in 1 - intruction 1 - clock mode by 3 - stage pipeline architecture parallel processing. it has the data flash memory area which can be written by software. in additio n, the on - chip debug function that is installed enables software debugging and programming. features cpu - 16- bit risc cpu (cpu name: nx - u16/100) - instruction system: 16 - bit length instruction ? instruction set: transfer, arithmetic operations, compar ison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on - chip debug function built in ? minimum instruction execution time 30.5 s (a t 32.768 khz system clock) 0.063 s (at 16 mhz system clock) internal memory ? flash memory (program area) rewrite count 100 cycles ml620q131: 8 kbyte (4k x 16 bits) ML620Q132: 16 kbyte (8k x 16 bits) ml620q133: 24 kbyte (12k x 16 bits) ml620q134: 8 kby te (4k x 16 bits) ml620q135: 16 kbyte (8k x 16 bits) ml620q136: 24 kbyte (12k x 16 bits) ? flash memory (data area) rewrite count 10,000 cycles 2 kbyte (1k x 16 bits) ? sram 2 kbyte (2k x 8 bits) interrupt controller - non - maskable interrupt source: 2 ( internal sources: back - up clock, wdt) - maskable interrupt sources: 30 (internal sources: 25, external sources: 5) - four interrupt levels and masking function time base counter - low - speed time base counter 1 ch annel watchdog timer ? non - maskable interrupt and reset (the first overflow generates an interrupt, and the second overflow generates a reset) ? free running ? overflow period: 4 types selectable (125 ms, 500 ms, 2 s, and 8 s at 32.768 khz)
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 2 / 33 timer s ? 8 bits x 10 ch (16 - bit configuration available) ? continuous timer mode/one - shot timer mode ? timer start/stop function by software/external trigger input pwm ? resolution 16 bits x 1 ch ? continuous pwm mode/one - shot pwm mode ? pwm start/stop function by software/external trigger input synchronous serial port ? master/slave selectable ? lsb first/msb first selectable ? 8 - bit length/16 - bit length selectable ? operation in the spi mode 0/3 ? overflow detection function uart ? full - duplex communication x 1 ch ? bit length, parity/no par ity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? internal baud rate generator i 2 c bus interface ? master x 1ch standard mode (100 kbit/s) and fast mode (400 kbit/s) are supported ? slave x 1ch standard mod e (100 kbit/s) and fast mode (400 kbit/s) are supported successive approximation type a/d converter ? 10- bit a/d converter ? ml620q131/ ML620Q132/ ml620q133 : input 6 ch ? ml620q134/ ml620q135/ml620q136 : input 8 ch analog comparator ? operation vol tage range: v dd = 1.8 to 5.5 v ? hysteresis width (only comparator 0): 20 mv (typ.) ? interrupts allow edge selection and sampling selection duty measurement circuit ? duty ratio measurement by inputting pwm signals with frequencies from 2 khz to 64 kh z ? duty measurement interrupt: 4 types selectable (64 s, 0.51 ms, 1.09 ms, 2.18 ms) general - purpose ports ?i including secondary functions ?j ? input - only port 1 ch (including secondary functions, also used by the on - chip debug pin) ? i/o port ml620q131/m l620q132/ml620q133: 10 ch (including secondary functions) ml620q134/ml620q135/ml620q136: 14 ch (including secondary functions)
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 3 / 33 reset ? reset_n pin reset ? reset by power - on detection ? reset by the watchdog timer (wdt) overflow ? reset by ram parity er ror (enable/disable can be selected) ? reset by voltage level detection 0 (vls0) (enable/disable can be selected) ? reset by voltage level detection 1 (vls1) (enable/disable can be selected) ? reset by prohibition program address change voltage l evel d etect function ? 2 ch ? threshold voltage: 12 values selectable ? interrupt generation or reset generation can be selected clock ? low - speed clock internal low - speed rc oscillation (32.768 khz) ? high - speed clock pll oscillation @ internal high - speed rc oscillation (32 mhz*1) high - speed crystal oscillation (4 mhz) pll oscillation @ high - speed crystal oscillation (32 mhz*1*2) ? selection of high - speed clock mode by software pll oscillation @ internal high - speed rc oscillation mode (16 mhz) high - speed crys tal oscillation mode (4 mhz) pll oscillation @ high - speed crystal oscillation mode (16 mhz) *1 ) 32 mhz can be used only as the pwmc clock. the maximum frequency of the system clock is 16 mhz. *2 ) to use the high - speed crystal oscillation and pll os cillation @ high - speed crystal oscillation, be sure to connect the high - speed crystal (4 mhz). power management ? halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) ? stop mode: stops the low - speed oscillation and high - speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high - speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, or 1/16 of the oscillation clock) ? block control function: powers down (reset registers and stop clock supply) the circuits of unused function blocks
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 4 / 33 sh ipment ? 16- pin plastic ssop ml620q131 - xxxmb (works: ml620q131 - nnnmb) ML620Q132 - xxxmb (works: ML620Q132 - nnnmb) ml620q13 3 - xxxmb (works: ml620q13 3 - nnnmb) xxx: rom code number ? 16- pin wqfn ml620q131 - xxxgd (works: ml620q131 - nnngd) ML620Q132 - xxxgd (works: ML620Q132 - nnngd) ml620q133 - xxxgd (works: ml620q133 - nnngd) xxx: rom code number ? 20- pin plastic tssop ml620q134 - xxx td (works: ml620q134 - nnn td ) ml620q135 - xxx td (works: ml620q135 - nnn td ) ml620q136 - xxx td (works: ml620q136 - nnn td ) xxx: rom cod e number guaranteed operating range ? operating temperature: - 40 to 105 c ? operating voltage: v dd = 1.6 to 5.5 v the difference of ml620q13 0 series is shown below. feature ml620q131 ML620Q132 ml620q133 ml620q134 ml620q135 ml620q136 shipment 16 - pin ssop/ 16 - pin wqfn 20- pin tssop flash capacity (program area) 8 kb 16 kb 24 kb 8 kb 16 kb 24 kb number of input channels for successive approximation type a/d converter 6 ch 8 ch number of input - only ports 1 (also used by the on - chip debug pin) 1 (also used by the on - chip debug pin) number of i/o ports 10 14
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 5 / 33 block diagram ml620q1 3 1/ML620Q132/ml620q133 block diagram ? * ? indicates the secondary, tertiary or quarternary function. figure 1 - 1 ml 620q13 1/ML620Q132/ml620q133 block diagram program memory (flash) 8/16/24kbyte ram 2k byte interrupt controller cpu (nx - u16/100) timing controller ea sp on - chip ice instruction decoder bus controller instruction register tbc int 3 int 1 wdt 8 bit timer 10 int 1 pwm gpio int 5 data - bus test 0 reset n osc osc 0* osc 1* lsclk* outclk* power v ddl reset & test alu epsw1 ?` 3 psw elr1 ?` 3 lr ecsr1 ?` 3 dsr/csr pc greg 0 ?` 15 v dd v ss analog comparator 2 cmp0p* cmp0m* int 2 sa- adc int 1 ain0 to ain 5 * test1_n int 10 pwmc* vls i2c master/slave sda0* int 2 scl0* uart rxd0* int 2 txd0* p a0 to p a 2 int 2 int 1 p b0 to p b7 rxd1* txd1* ssiox1 sck0* int 1 sin0* sout0* cmp 1 p* dme int 1
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 6 / 33 ml620q1 34/ml620q135/ml620q136 block diagram ? * ? indicates the secondary, tertiary or quarternary function. figure 1 - 2 ml620q13 4 /ml620q13 5 /ml620q13 6 block diagram program memory (flash) 8/16/24kbyt e ram 2k byte interrupt controller cpu (nx - u16/100) timing controller ea sp on - chip ice instruction decoder bus controller instruction register tbc int 3 int 1 wdt 8 bit timer 10 int 1 pwm gpio int 5 data - bus test 0 reset n osc osc 0* osc 1* lsclk* outclk* power v ddl reset & test alu epsw1 ?` 3 psw elr1 ?` 3 lr ecsr1 ?` 3 dsr/csr pc greg 0 ?` 15 v dd v ss analog comparator 2 cmp0p* cmp0m* int 2 sa- adc int 1 ain0 to ain 7 * test1_n int 10 pwmc* vls i2c maste r/slave sda0* int 2 scl0* uart rxd0* int 2 txd0* p a0 to p a6 int 2 int 1 p b0 to p b7 rxd1* txd1* ssiox1 sck0* int 1 sin0* sout0* cmp 1 p* dme int 1
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 7 / 33 pin configuration pin layout of ml620q131/ML620Q132/ml620q133 16pin ssop pa ckage figure 2 pin layout of ml620q131/ML620Q132/ml620q133 16pin ssop package reset_n test1_n pb3 / osc1 / cmp0nout pa2 / exi2 / test0 pb6 / ain4 / rxd1 lsclk / tmfout / sda 8 7 6 5 4 3 2 1 pb2 / osc0 / cmp0pout pb1 / exi5 / ain3 / txd1 / txd0 / cmp0out pb0 / exi4 / ain2 / rxd0 / pwmc / scl / cmp1out/duti 9 10 11 12 13 14 15 16 pa0 / led0 / exi0 / ain0 / rxd1 / pwmc / outclk / sda pb7 / led 1 / ain5 / txd1 / scl / pwmc/duti v dd v ss v ddl pb5 / rxd0 / cmp0m outclk / tmjout / sck0 pb4 / cmp0p / txd1 / txd0 / sin0 pa1 / exi1 / ain1 / cmp1p / lsclk / sout0
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 8 / 33 pin layout of ml620q131/ML620Q132/ml620q133 16pin wqfn pa ckage figure 3 pin layout of ml620q131/ML620Q132/ml620q133 16pin wqfn package 1 pb6 / ain4 / rxd1 lsclk / tmfout / sda 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 pa2 / exi2 / test0 pb4 / cmp0p / txd1 / txd0 / sin0 pa1 / exi1 / ain1 / cmp1p / lsclk / sout0 pa0 / led0 / exi0 / ain0 / rxd1 / pwmc / outclk / sda pb7 / led1 / ain5 / txd1 / scl / pwmc / duti pb2 / osc0 / cmp0pout pb3 / osc1 / cmp 0nout pb5 / rxd0 / cmp0m / outclk / tmjout / sck0 v dd v ss pb0 / exi4 / ain2 / rxd0 / pwmc / scl / cmp1out/duti pb1 / exi5 / ain3 / txd1 / txd0 / cmp0out reset_n test1_n v ddl
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 9 / 33 pin layout of ml620q134/ml620q135/ml620q136 20pin tssop pa ckage figure 4 pin layout of ml620q134/ml620q135/ml620 q136 20pin tssop package reset_n test1_n pb3 / osc1 / cmp0nout pa2 / exi2 / test0 pb6 / ain4 / rxd1 lsclk / tmfout / sda 10 9 8 7 4 3 2 1 pb2 / osc0 / cmp0pout pb1 / exi5 / ain3 / txd1 / txd0 / cmp0out pb0 / exi4 / ain2 / rxd0 / pwmc / scl / cmp1out / duti 11 12 13 14 17 18 19 20 pa0 / led0 / exi0 / ain0 / rxd1 / pwmc / outclk / sda pb7 / led1 / ain5 / txd1 / scl / pwmc/duti v dd v ss v ddl pb5 / rxd0 / cmp0m outclk / tmjout / sck0 pb4 / cmp0p / txd1 / txd0 / sin0 pa1 / exi1 / ain1 / cmp1p / lsclk / sout0 6 5 15 16 pa3 / ain6 / sda pa5 / sck0 / scl pa4 / ain7 / sin0 pa6 / sout0
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 10/ 33 pin list table 1 pin list pad no. (16pin ssop) pad no. (16pin wqfn) pad no. (20pin tssop) primary function secondary function tertiary function quartic function pin name i/o feature pin name i/o feature pin name i/o feature p in name i/o feature 14 12 18 v dd i/o positive power supply pin input/output ? ? ? ? ? ? ? ? ? 12 10 16 v ddl i/o power supply pin for internal logic (internal generation) ? ? ? ? ? ? ? ? ? 13 11 17 v ss i/o negative power supply pin input/output ? ? ? ? ? ? ? ? ? 5 3 7 reset_n i reset input pin ? ? ? ? ? ? ? ? ? 6 4 8 test1_n i input pin for testing ? ? ? ? ? ? ? ? ? 16 13 20 pa0/ led0/ exi0/ ain0/ rxd1 i/o i/o port/ led drive external interrupt 0/ ad input 0/ uart1 reception pwmc o pwmc output outclk o high - spe ed clock output sda i/o i 2 c data i/o 9 8 11 pa1/ exi1/ ain1/ cmp1p i/o i/o port/ external interrupt 1/ ad input 1/ comparator 1 non - inverting input ? ? ? lsclk o low - spe ed clock output sout0 o ssio data output 7 6 9 pa2/ exi2/ test0 i input port / external interrupt 2/ input pin for testing ? ? ? ? ? ? ? ? ? ? ? 5 pa3/ ain6 i/o i/o port/ ad input 6 ? ? ? sda i/o i 2 c data i/o ? ? ? ? ? 15 pa4/ ain7 i/o i/o port/ ad input 7 sin0 i ssio data input ? ? ? ? ? ? ? ? 6 pa5 i/o i/o port sck0 i/o ssio c lock i/o scl i/o i 2 c clock i/o ? ? ? ? ? 14 pa6 i/o i/o port sout0 o ssio data output ? ? ? ? ? ? 3 1 3 pb0/ exi4/ ain2/ rxd0/ duti i/o i/o port/ external interrupt 4/ ad input 2/ uart0 reception/ duty measurement pwmc o pwmc output scl i/o i 2 c clock i/o cmp1 out o cmp1 output 4 2 4 pb1/ exi5/ ain3 i/o i/o port/ external interrupt 5/ ad input 3 txd1 o uart1 transmission txd0 o uart0 transmis sion cmp0 out o cmp0 output 1 16 1 pb2 i/o i/o port osc0 i high - speed oscillation ? ? ? cmp0pout o cmp0p output 2 15 2 pb3 i/o i/o port osc1 o high - speed oscillation ? ? ? cmp0nout o cmp0n output
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 11/ 33 pad no. (16pin ssop) pad no. (16pin wqfn) pad no. (20pin tssop) primary function secondary function tertiary function quartic function pin name i/o feature pin name i/o feature pin name i/o feature p in name i/o feature 10 7 12 pb4/ cmp0p i/o i/o port/ comparator 0 non - inverting input txd1 o uart1 transmission txd0 o uart0 transmis sion sin0 i ssio data input 11 9 13 pb5/ rxd0/ cmp0m i/o i /o port/ uart0 reception/ comparator 0 inverting input outclk o high - speed clock output tmj out o timer j output sck0 i/o ssio clock i/o 8 5 10 pb6/ ain4/ rxd1 i/o i/o port/ ad input 4/ uart1 reception lsclk o low - speed clock output tmf out o timer f out put sda i/o i 2 c data i/o 15 14 19 pb7/ led1/ ain5/ duti i/o i/o port/ led drive ad input 5/ duty measurement txd1 o uart1 transmission scl i/o i 2 c clock i/o pwmc o pwmc output
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 12/ 33 pin description table 2 pin description (1/ 4 ) pin name i/o description pri mary/ secondary/ tertiary/ quartic logic system reset_n i reset input pin. when this pin is set to a "l" level, system reset mode is set and the internal section is initialized. when this pin is set to a "h" level subsequently, program execution starts. the reset_n pin does not have an internal pull - up resistor. ? negative osc0 i crystal connection pin for the high - speed clock. a crystal oscillator is connected to this pin (4 mhz max.), and capacitors c dh and c gh (see measurement circuit 1) are connected between this pin and v ss . this pin is used as the secondary function of the pb2 and pb3 pins. secondary ? osc1 o secondary ? lsclk o low - speed clock output. this pin is used as the tertiary function of the pa1 pin or the secondary function of the pb6 p in. secondary/ tertiary ? outclk o high - speed clock output pin. this pin is used as the tertiary function of the pa0 pin or the secondary function of the pb5 pin. tertiary ? general - purpose input port pa2 i general - purpose input port. ? positive genera l - purpose input/output port pa0 to pa 1 pb0 ~ pb7 i/o general - purpose input/output port. this cannot be used as the general input/output port when used as the secondary to quartic functions. ? positive pa3 to pa6 i/o general - purpose input/output port. this cannot be used as the general input/output port when used as the secondary to quartic functions. not available in ml620q131/ML620Q132/ml620q133. ? positive serial (uart) txd0 o uart0 transmit pin. this pin is used as the tertiary function of the pb1 and pb4 pins. tertiary positive txd1 o uart1 t ransmit pin. this pin is used as the secondary function of the pb1, pb4, and pb7 pins. secondary positive rxd0 i uart0 receive pin. this pin is used as the primary function of the pb0 and pb5 pins. primary positive rxd1 i uart1 receive pin. this pin is u sed as the primary function of the pa0 and pb6 pins. primary positive i 2 c bus interface sda i/o nmos open drain pin for i 2 c data input/output. this pin is used as the quartic function of the pa0 pin, the tertiary function of the pa3 pin, or the quartic f unction of the pb6 pin. a pull - up resistor is connected externally. tertiary/ quartic positive scl i/o nmos open drain pin for i 2 c clock input/output. this pin is used as the tertiary function of the pa5 pin, the tertiary function of the pb0 pin, or the t ertiary function of the pb7 pin. a pull - up resistor is connected externally. tertiary positive
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 13/ 33 table 2 pin description ( 2 / 4 ) pin name i/o description primary/ secondary/ tertiary/ quartic logic synchronous serial (ssio) sin i synchronous serial data i nput pin. this pin is used as the secondary function of the pa4 pin or the quartic function of the pb4 pin. secondary/ quartic positive sck0 i/o high - speed clock input pin. this pin is used as the secondary function of the pa5 pin or the quartic function of the pb5 pin. secondary/ quartic ? sout0 o high - speed clock output pin. this pin is used as the quartic function of the pa1 pin or the secondary function of the pa6 pin. secondary/ quartic positive pwm pwmc o pwmc output pin. this pin is used as the s econdary function of the pa0 and pb0 pins or the quartic function of the pb7 pin. secondary/ quartic positive/ negative external interrupt exi0 to 2 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each b it by software. this pin is used as the primary function of the pa0 to pa2 pins. primary positive/ negative exi4,5 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. this pin is used as the primary function of the pb0 and pb1 pins. primary positive/ negative timer tntg i external trigger input pin of the timer 0, timer 1, timer e, timer f, timer g, timer h, timer i, timer j, timer k, or timer l. this pin is used as the primary function of the pa0 to pa2 and pb0 to pb7 pins. primary ? tmjout o timer j output pin. this pin is used as the tertiary function of pb5. tertiary positive tmfout o timer f output pin. this pin is used as the tertiary function of pb6. tertiary positive led drive led0, 1 o pins for led driving. allocated to the primary function of the p a0 and pb7 pins. primary positive/ negative
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 14/ 33 table 2 pin description ( 3 / 4 ) pin name i/o description primary/ secondary/ tertiary/ quartic logic successive approximation type a/d converter ain0 i ch0 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa0 pin. primary ? ain1 i ch1 analog input for successive approximation type a/d converter. this pin is used as the primar y function of the pa1 pin. primary ? ain2 i ch2 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb0 pin. primary ? ain3 i ch3 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb1 pin. primary ? ain4 i ch4 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb6 pin. primary ? ain5 i ch5 analog input for successive approximatio n type a/d converter. this pin is used as the primary function of the pb7 pin. primary ? ain6 i ch6 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa3 pin. not available in ml620q131/ML620Q132 /ml620q133. primary ? ain7 i ch 7 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa4 pin. not available in ml620q131/ML620Q132/ml620q133. primary ? comparator cmp0p i comparator 0 non - invert ing input. this pin is used as the primary function of the pb4 pin. primary ? cmp0m i comparator 0 inverting input. this pin is used as the primary function of the pb5 pin. primary ? cmp0out o comparator 0 output pin. this pin is used as the quartic func tion of the pb1 pin. quartic ? cmp0pout o comparator 0 output pin. this pin is used as the quartic function of the pb2 pin. quartic ? cmp0nout o comparator 0 output pin. this pin is used as the quartic function of the pb3 pin. quartic ? cmp1p i comparat or 1 non - inverting input. this pin is used as the primary function of the pa1 pin. primary ? cmp1out o comparator 1 output pin. this pin is used as the quartic function of the pb0 pin. quartic ? duty measurement circui t duti i pwm waveform input for the duty measurement circuit. this pin is used as the primary function of the pb0 and pb7 pins . primary ?
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 15/ 33 table 2 pin description ( 4 / 4 ) pin name i/o description primary/ secondary/ tertiary/ quartic logic for testing test0 i input pin for testing. this pin is used as the primary function of the pa2 pin. ? positive test1_n i input pin for testing. a pull - up resistor is internally connected. ? negative power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? power supply pin for internal logic (internally generated). capacitor c l (see measurement circuit 1) is connected between this pin and v ss . ? ?
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 16/ 33 termination of unused pins table 3 termination of unused pins pin recommended pin termination reset_n v dd tes t1_n open pa0 to pa1 open pa2/test0 v ss pa3 to pa6 open p b0 to pb7 open note: for unused input ports or unused input/output ports, if the corresponding pins are configured as high - impedance inputs and left open, the supply current may become excessi vely large. therefore, it is recommended to configure those pins as either inputs with a pull - down resistor/pull - up resistor or outputs.
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 17/ 33 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25c - 0.3 to + 6.5 v power supply voltage 2 v ddl ta = 25c - 0.3 to + 2.0 v input voltage v in ta = 25c - 0.3 to v dd +0.3 v output voltage v out ta = 25c - 0.3 to v dd +0.3 v output current 1 (pa0 to pa1) (p a3 t o p a6)* (p b0 to p b7) i out1 ta = 25c - 12 to +11 ma output current 2 (pa0 ) (p b7) i out 2 ta = 25c when n - channel open drain output mode is selected - 12 to + 20 ma power dissipation pd ta = 25c 1 w storage temperature t stg D - 55 to +150 c * : ml620q131/ ML620Q132/ ml620q133 do not ha ve the peripherals. recommended operating conditions (v ss = 0v) parameter symbol condition range unit operating temperature t op D - 4 0 to + 105 c operating voltage v dd D 1.6 to 5 . 5 v operating frequency (cpu) f op v dd = 1.6 to 5.5v 30 k to 32.768k hz v dd = 1.8 to 5.5v 30 k to 16m high - speed crystal oscillation frequency f xt h v dd = 1.8 to 5.5v 4.0m hz high - speed crystal oscillation external capacitor c dh use nx8045ge ( nihon dempa kogyo corp. ) 16 pf c gh 16 capacitor externally connected to v ddl pin c l D 2.2 30% m f flash memory operating conditions (v ss = 0v) parameter symbol condition range unit operating temperature t op data flash memory, at write/erase - 4 0 to + 105 c flash rom, at write/erase 0 to + 40 operating voltage v dd at write/erase 1.6 to 5 . 5 v maximum rewrite count c epd data f lash 10,000 times c ep p program flash 100 erase unit D chip erase all area D D block erase program flash 4 kb data flash 2 kb D sector erase 1 kb erase time D chip erase, block erase, sector erase 100 ms write unit D D 1 word (2 bytes) D write time (max.) D 1 word (2 bytes) 40 m s data retention period y dr D 15 years
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 18/ 33 dc characteristics conditions (1/5) ( v dd = 1 . 6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) param eter symbol condition min. typ. max. unit measur ing circuit low - speed rc oscillator frequency f rcl ta= +25 c t yp - 1% 32.768k t yp +1% hz 1 ta= - 40 to 85c t yp - 2.5% 32.768k t yp +2.5% hz ta= - 40 to 105c t yp -3% 32.768k t yp +3% hz pll oscillation f requency * 1 f pll ta= - 20 to 85c , v dd = 1.8 to 5.5v t yp -1% 32 t yp +1% mhz ta= -40c to +105 c , v dd = 1.8 to 5.5v t yp - 1.5% 32 t yp +1.5% mhz low - speed rc oscillation start time* 1 t rcl D D D 65 m s high - speed rc oscillation start time* 1 t rch v dd = 1.8 to 5.5v D D 5 m s high - speed crystal oscillation start time* 1 t xth v dd = 1.8 to 5.5v D 2 20 ms pll oscillation start time t pll v dd = 1.8 to 5.5v D D 2 ms reset pulse width p rst D 100 D D m s reset noise rejection pulse width p nrst D D D 0. 4 power on reset rising time t por D D D 10 ms * 1 : 2048 clock average. the cpu clock is max. f pll /2. * 2 : use 4m hz crystal oscillator nx8045ge ( nihon dempa kogyo corp. ) reset pulse width (p rst ) power on reset v dd rising time (t por ) reset_n p rst vil1 vil1 v dd t por 1.8v 0v
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 19/ 33 dc characteristics conditions (2/5) ( v dd = 1.6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit vls0 threshold voltage v vls0 vls03 to 0 = 00h rise 1.64 1.67 1.70 v 1 fall 1.60 1.63 1.66 vls03 to 0 = 01h rise 1.74 1.77 1.81 fall 1.70 1.73 1.77 vls03 to 0 = 02h rise 1.84 1.88 1.91 fall 1.80 1.84 1.87 vls03 to 0 = 03h rise 1.94 1.98 2.02 fall 1.90 1.94 1.98 vls03 to 0 = 04h rise 2.05 2.09 2.13 fall 2.00 2.04 2.08 vls03 to 0 = 05h rise 2.45 2.50 2.55 fall 2.40 2.45 2.50 vls03 to 0 = 06h rise 2.56 2.61 2.66 fall 2.50 2.55 2.60 vls03 to 0 = 07h rise 2.66 2.71 2.76 fall 2.60 2.65 2.70 vls03 to 0 = 08h rise 2.76 2.81 2.87 fall 2.70 2.75 2.81 vls03 to 0 = 09h rise 2.86 2.92 2.97 fall 2.80 2.86 2.91 vls03 to 0 = 0ah rise 2.96 3.02 3.08 fall 2.90 2.96 3.02 vls03 to 0 = 0bh rise 4.01 4.09 4.17 fall 3.90 3.98 4.06 vls1 threshold voltage v vls1 vls13 to 0 = 00h 1.60 1.63 1.66 vls13 to 0 = 01h 1.70 1.73 1.77 vls13 to 0 = 02h 1.80 1.84 1.87 vls13 to 0 = 03h 1.90 1.94 1.98 vls13 to 0 = 04h 2.00 2. 04 2.08 vls13 to 0 = 05h 2.40 2.45 2.50 vls13 to 0 = 06h 2.50 2.55 2.60 vls13 to 0 = 07h 2.60 2.65 2.70 vls13 to 0 = 08h 2.70 2.75 2.81 vls13 to 0 = 09h 2.80 2.86 2.91 vls13 to 0 = 0ah 2.90 2.96 3.02 vls13 to 0 = 0bh 3.90 3.98 4.06
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 20/ 33 dc characteristics conditions (3/5) ( v dd = 1.6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit comparator0 same phase input voltage range v cmr v dd = 1.8 to 5 .5v 0.1 D v dd - 1.5 v 4 comparator0 hysteresis v hysp ta = 25 ?? , v dd = 5.0v 10 20 30 mv v dd = 5.0v 5 20 35 comparator0 input offset v cm of ta = 25 ?? , v dd = 5.0v D D 7 comparator reference voltage error * 3 v cmref ta = 25 ?? v dd = 1.8 to 5.5v -25 D 25 v dd = 1.8 to 5.5v -50 D 50 supply current 1 idd1 cpu is in stop state . low - speed oscillation is stopped. v dd =5.0v ta = -40 to +105 ?? D 1 22 m a 1 ta = -40 to +85 ?? D 1 9 supply current 2 idd2 internal rc oscillating. cpu is in halt state (ltbc,wbc: op erating *1 ). high - speed oscillation is stopped. v dd =3.0v ta = -40 to +105 ?? D 3.5 26 supply current 3 idd3 cpu : running at 32 khz * 2 high - speed oscillation is stopped. v dd =3.0v ta = -40 to +105 ?? D 13 42 supply current 4 idd4 cpu : running at 16m hz pll o scillating mode used high - speed crystal oscillation * 2 vdd= 5 .0v D 4.5 5.5 ma supply current 5 idd5 cpu : running at 16m hz pll oscillating mode used high - speed rc oscillation * 2 vdd= 5 .0v D 4.5 5.5 * 1 : ltbc and wdt is operating, significant bits of blkcon0 to blkcon 7 registers are all ?1? * 2 : cpu running rate is 100% * 3 : including comparator input offset voltage
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 21/ 33 dc characteristics conditions (4/5) ( v dd = 1.6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit output voltage 1 (pa0 to pa1) (p a3 to p a6)* (p b0 to p b7) voh1 ioh1 = - 0.5ma v dd - 0.5 D D v 2 vol1 iol1 = +0.5ma D D 0.5 output voltage 2 (pa0 ) (p b7) vol2 when n - channel open drain output mode is selected iol2 = + 10 ma v dd 3 5.0 v D D 0.5 iol2 = + 8 ma v dd 3 3.0 v D D 0.5 iol 3 = +3 ma v dd 3 2.0 v D D 0. 4 iol 3 = +2 ma 2.0 v > v dd 3 1.8 v D D vdd* 0.2 output leakage current (pa0 to pa1) (p a3 to p a6)* ( p b0 to p b7) iooh voh = v dd (in high - impedance state) D D 1 m a 3 iool vol = v ss (in high - impedance state) - 1 D D input current 1 (reset_n) iih1 vih1 = v dd D D 1 4 iil1 vil 1 = v ss - 1 D D input current 2 (test1_n) iih 2 vih 2 = v dd D D 1 iil 2 vil 2 = v ss - 1 500 - 300 - 20 input current 3 (pa0 to pa1) (p a2/test0) (p a3 to p a6)* (p b0 to p b7) iih 3 vih 3 = v dd ( when pulled down ) 2 30 2 5 0 iil 3 vil 3 = v ss ( when pulled up ) - 2 5 0 - 30 - 2 iih 3 z vih 3 = v dd (in high - impedance state) D D 1 iil 3 z vil 3 = v ss (in high - impedance state) -1 D D * : ml620q131/ ML620Q132/ ml620q133 do not have the peripherals.
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 22/ 33 dc characteristics conditions (5/5) ( v dd = 1.6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit input voltage 1 (reset_n) (test1_n) (pa0 to pa1) (p a2/test0) (p a3 to p a6)* ( p b0 to p b7) vih 1 D 0. 7 v dd D v dd v 5 vil 1 D 0 D 0. 3 v dd input pin capacitance (reset_n) (test1_n) (pa0 to pa1) (p a2/test0) (p a3 to p a6)* (p b0 to p b7) cin f = 10khz v rms = 50mv ta = 25 c D D 10 pf D * : ml620q131/ ML620Q132/ ml620q133 do not have the peripherals.
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 23/ 33 measuring circuit 1 measuring circuit 2 input pins v vih vil output pins ( *2 ) ( *1 ) v dd v ddl v ss (* 1 ) input logic circuit to determine the sp ecified measuring conditions. (* 2) measured at the specified output pins. a v dd v ss c v ?f 2.2 f c l ?f 2.2 f c gh ?f 16 p f c dh ?f 16 p f 4mhz crystal ?f nx8045ge ( nihon dempa kogyo corp.) c v 4mhz crystal c gh c d h pb2/osc0 pb3/osc1 c l v ddl
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 24/ 33 measuring circuit 3 measuring circuit 4 measuring circuit 5 vih vil *1: input logic circuit to determine the specified measuring conditions. v dd v ddl v ss waveform monitoring output pins input pins (*1 ) a * 3 : measured at the specified input pins. ( * 3) v dd v ddl v ss output pins input pins input pins a vih vil (* 1 ) input logic circuit to determine the specified measuring conditions. (* 2) measured at the specified output pins. ( *2 ) (*1) v dd v ddl v ss outpu t pins
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 25/ 33 ac characteristics (external interrupt) ( v dd = 1.6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled ( mie = 1 ), cpu is executing nop instruction 2.5 lsclk D 3.5 lsclk m s t nul pa0 to pa2, pb0 to pb1 ( rising - edge interrupt ) ( falling - edge interrupt ) ( both - edge interrupt ) t nul t nul pa0 to pa2, pb0 to pb1 pa0 to pa2, pb0 to pb1
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 26/ 33 ac characteristics (synchronous serial port) ( v dd = 1. 6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition min. typ. max . unit sck input cycle (slave mode) t scyc D 1 D D m s sck output cycle (master mode) t scyc D D sck ( * 1) D s ec sck input pulse width (slave mode) t sw high - speed oscillation stopped 0. 4 D D m s during high - speed oscillation 200 D D ns sck output pulse wi dth (master mode) t sw D sck ( * 1) 0.4 sck ( * 1) 0.5 sck ( * 1) 0.6 s ec sout output delay time (slave mode) t sd D D D 360 ns sout output delay time (master mode) t sd D D D 160 ns sin input setup time (slave mode) t ss D 8 0 D D ns sin input setup time ( master mode) t ss D 180 D D ns sin input hold time t sh D 8 0 D D ns *1: clock period selected by s 0 ck3 ? 0 of the serial port n mode register (sio 0 mod 1 ) t sd sck0* sin0* sout0 *: indicates the secondary function of the corresponding port. t sd t ss t sh t sw t sw t scyc
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 27/ 33 ac characteristics (i2c bus interface: standard mode 100khz) ( v dd = 1. 6 to 5 .5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition rating unit min. typ. max. scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? m s scl ?l ? level time t low ? 4.7 ? ? m s scl ?h ? level time t high ? 4.0 ? ? m s scl setup time (restart condition) t su:sta ? 4.7 ? ? m s sda hold time t hd:dat ? 0 ? ? m s sda setup time t su:dat ? 0.25 ? ? m s sda setup time (stop condition) t su:sto ? 4.0 ? ? m s bus - free time t buf ? 4.7 ? ? m s ac characteristics (i2c bus interface: fast mode 400khz) ( v dd = 1. 6 to 5.5 v, v ss = 0v, ta = - 40 to + 105 c , unless otherwise specified) parameter symbol condition rating unit min. typ. max. scl clock frequency f scl ? 0 ? 400 khz scl hold time (star t/restart condition) t hd:sta ? 0.6 ? ? m s scl ?l ? level time t low ? 1.3 ? ? m s scl ?h ? level time t high ? 0.6 ? ? m s scl setup time (restart condition) t su:sta ? 0.6 ? ? m s sda hold time t hd:dat ? 0 ? ? m s sda setup time t su:dat ? 0.1 ? ? m s sda setu p time (stop condition) t su:sto ? 0.6 ? ? m s bus - free time t buf ? 1.3 ? ? m s note: current drive ability of pa 3 , p a5 , p b0 and pb6 in n - ch open drain mode is lower than that of pa0 and pb7. therefore, the fast mode (400kbps) cannot be avail able when pa5 or pb0 is set as scl function and when pa3 or pb6 is set as sda function. for more details, see the characteristics of vol1 and vol2 in dc characteristics conditions (4/5) . scl sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su :dat t hd:dat t su:sto
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 28/ 33 successive approximation type a/d converter parameter symbol condition min. typ. max. unit resolution n D D D 10 bit s integral non - linearity error inl 2. 7 v v dd 5.5 v - 4 D +4 lsb 2. 2 v v dd ?? 2.7 v - 6 D + 6 1.8 v v dd ?? 2.2 v - 10 D + 10 di fferential non - linearity error d nl 2. 7 v v dd 5.5 v - 3 D +3 2. 2 v v dd ?? 2.7 v - 5 D + 5 1.8 v v dd ?? 2.2 v - 9 D + 9 zero - scale error v off ri 5k ?? - 6 D + 6 full - scale error fse ri 5k ?? - 6 D + 6 input impedance r i D D D 5k ?? a/d operating voltage v dd D 1.8 D 5.5 v conversion time t conv cpu works in pll oscillation mode sack bit = 0 2. 7 v v dd 5.5 v D 13. 67 D s cpu works in pll oscillation mode sack bit = 1 1.8 v v dd 5.5 v D 4 1.26 D note: ml620q131/ml620q1 32/ml620q133 do no have ain7 and ain6. a v dd v ddl v ss analog input 2.2 f - r i 5k ?? ain0 to ain7 0.1 f + 2.2 f
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 29/ 33 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact lapis semiconductor ?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16 pin ssop notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mountin g, contact a rohm sales office for t he product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 30/ 33 16pin wqfn notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for th e product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times ).
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 31/ 33 20 pin tssop notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow moun ting, contact a rohm sales office for t he product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 32/ 33 r evision history document no. date page description previous edition current edition f edl 620q1 3 0 -01 nov 12, 201 5 ? ? fromal 1 st revision fedl620q130 -02 may 12, 2016 17 17 corrected condition of sector erase. 20 20 corrected condition of supply current.
f ed l620q130 - 0 2 ml620q1 3 1/2/3/4/5/6 33/ 33 notes 1) the information contained herein is subject to change without notice. 2) although lapis semicondu ctor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. therefore, in order to prevent personal injury or fire arising from failur e, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail - safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circuit constants and any other information contained herein are provided only to illustrat e the standard usage and operations of the products.the peripheral conditions must b e taken into account when designing circuits for mass production. 4) the technical information specified herein is intended only to show the typical functions of the products and examples of application circuits for the products. no license, expressly or im plied, is granted hereby under any intellectual property rights or other rights of lapis semiconductor or any third party with respect to the information contained in this document; therefore lapis semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) the products are intended for use in general electronic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non - compliance with the recommended usage conditions and specifications contained herein. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such information is error - free and lapis semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, including rohs compatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non - compliance with any applicable la ws or regulations. 12) when providing our products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the us ex port administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in whole, may not be reprinted or reproduced without prior consent of lapis semiconductor. copyright 2015- 201 6 lapis semiconductor co., ltd. 2 - 4 - 8 shinyokohama, kouhoku - ku, yokohama 222 - 8575, japan http://www.lapis - semi.com/en/

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